1. Field Of The Invention
The present invention relates to packages (or microstacks) for mounting and interconnecting semiconductor chips; more particularly, to packages for housing high speed, high power semiconductor chips in a three-dimensional array, providing interconnections between the chips, and for dissipating the heat generated by the chips.
2. Description Of The Related Art
Many advances have been made in reducing the size of semiconductor devices, and thus in increasing the number of semiconductor devices on a chip. Accordingly, there has been an increase in the number of gates on each chip, in the number of leads (bonding pads) emanating from each chip, and in the electrical power handled by and heat created by each chip. These increases in densities have required increases in the number of connections between chips, and thus larger overall packages. As used herein, the term "chip(s)" refers to an encapsulated die having bonding pads provided thereon, and the term "package(s)" refers to devices for housing and/or interconnecting plural semiconductor chips. Dissipating the heat generated by semiconductor chips having large power handling capabilities has required larger packages.
Two different types of packages have been used to provide connections between the various chips in a package (or interconnect system), so-called "two-dimensional packages" and "three-dimensional packages." In a two-dimensional package individual leads connecting semiconductor chips provided on the exterior of the package pass in the x, y and z directions within the package. Such a package usually comprises a plurality of wafers provided in a stack with x and y interconnects on the surface of or contained in the wafers and z direction interconnections passing through the wafers.
In a three-dimensional package, semiconductor chips are mounted within the package; semiconductor chips may also be provided on the exterior of the package. Accordingly, a three-dimensional package may incorporate a larger number of semiconductor chips, requiring a larger number of interconnections and greater cooling capabilities. Moreover, the interconnect system becomes more complicated because of the limited areas where x, y and z direction connections can be provided.
To determine the relative capabilities of different packages or interconnect systems several standards are utilized. The most common standard for comparing the relative capabilities of interconnect systems is the number of interconnects per unit volume of package. A similar standard is the number of pins (or leads) per unit volume of package. Other methods of comparison include computing the package volume per chip and the number of gates per unit volume of package.
An example of a three-dimensional package is disclosed in U.S. Pat. No. 3,769,702, and an example of a two-dimensional package is illustrated in U.S. Pat. No. 3,705,332. Other U.S. Patents pertaining to packages for semiconductor chips include the following: U.S. Pat. No. 3,775,844; U.S. Pat. No. 3,813,773; U.S. Pat. No. 3,917,983; U.S. Pat. No. 4,095,867; U.S. Pat. No. 4,268,956; and U.S. Pat. No. 4,283,754.
The two and three-dimensional packages and interconnect systems illustrated in U.S. Pat. Nos. 3,705,332 and 3,769,702 utilize 50 mil. grids for the z-axis connections and have a pin density of approximately 940 pins per cubic inch.
Cooling the semiconductor chips sandwiched between wafers within a wafer stack becomes critical in three-dimensional packages. The factors to be considered in comparing the cooling needs and capabilities of various packages include the number of watts generated by each chip, the number of watts generated by the the total number of chips, the flow rate of coolant for each chip and for the package, and the thermal or temperature differential between the various semiconductor chips in the package. Prior liquid cooling systems often provide the same coolant to several chips serially. Thus, the coolant is warmed by each successive chip which it passes over and the ability of the coolant to dissipate heat diminishes for each successive chip. The last chip to receive the coolant will have a higher operating temperature than the first chip to receive the coolant. Such a temperature differential is detrimental to the operation of the overall system including the chips in question.
Other problems with prior packages are the large size and weight of the packages and the computers incorporating such packages. Conventional CPU weights approach 0.6 pounds per LSI chip.